IBM and Siemens Team on Nanostack Chip Research
IBM and Siemens announced research collaboration to advance IBM's 3D nanostack transistor architecture toward manufacturing beyond the current 7 angstrom node.
What you need to know
IBM, with Siemens, announced research aimed at advancing IBM's nanostack transistor architecture toward production. The collaboration combines IBM's semiconductor device work with Siemens' electronic design automation, process simulation and lithography expertise, focusing on design, simulation and lithography techniques for current and future nanostack generations.
- IBM announced the collaboration with Siemens on October 14, 2026, in Albany, NY.
- IBM says nanostack packs nearly 100 billion transistors into a fingernail-sized space at its 7 angstrom node.
- The work targets design, simulation and lithography advances for nanostack beyond the current node.
What the collaboration covers
IBM announced that it is working with Siemens on research to advance its nanostack architecture, a transistor design IBM unveiled earlier this year. The companies said the effort brings together IBM's semiconductor device work and Siemens' expertise in electronic design automation, process simulation, lithography optimization and manufacturing software.
The collaboration includes developing virtual models of nanostack to assess performance, optimize designs and address fabrication challenges before chips are built. IBM said its earlier demonstration showed the architecture is viable, and that further advances are needed to prepare it for manufacturing and production at scale.
The nanostack design
Nanostack is described by IBM as the industry's first known three-dimensional, nanosheet-based design that vertically stacks and staggers transistors. At its current 7 angstrom node, IBM says the design places nearly 100 billion transistors in a space the size of a fingernail and allows different material combinations within each stacked layer to tune performance and power efficiency.
IBM executives framed the platform as a way to shift device scaling from two dimensions to three, and Siemens executives described the work as targeting co-optimization among device physics, design software and manufacturing.
Does the IBM-Siemens collaboration mean nanostack chips are ready for production?
No. IBM said further advances are needed to prepare the architecture for manufacturing at scale. The collaboration targets design, simulation and lithography work for current and future nanostack generations.
Sources & context
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